1. Field of the Invention
The present invention relates to a memory cell circuit provided with independent select control lines and bit lines for output for use for writing and reading operations.
2. Description of the Related Art
FIG. 1 is a circuit diagram of an example of the configuration of a memory cell circuit as a related art.
As shown in FIG. 1, the memory cell circuit is configured as a static random access memory (SRAM) cell 1 comprised of an inverter 11 and an inverter 12 with inputs and outputs connected cross-wise, a read only circuit 2 comprised of an n-channel (N) metal oxide semiconductor (MOS) transistor for driving 21 and an NMOS transistor for access 22, the transistors 21 and 22 being connected in series between a bit line for reading R-BL and a ground line ( reference voltage source ), and a write only circuit 3 comprised of an NMOS transistor for writing 31 and an NMOS transistor for selecting 32, the transistors 31 and 32 being connected in series between a first memory node ND1 of the SRAM cell 1 and the ground line, and an NMOS transistor for writing 33 and an NMOS transistor for selecting 34, the transistors 33 and 34 being connected in series between a second memory node ND2 of the SRAM cell 1 and the ground line.
A gate electrode of the NMOS transistor for driving 21 of the read only circuit 2 is connected to the first memory node ND1 as the output node of the SRAM cell 1, and a gate electrode of the NMOS transistor for access 22 is connected to a word line for reading R-WL. A gate electrode of the NMOS transistor for writing 31 of the write only circuit 3 is connected to a bit line for writing high level data W-BLH, a gate electrode of the NMOS transistor 33 is connected to a bit line for writing low level data W-BLL, and gate electrodes of the NMOS transistors for selecting 32 and 34 are connected to a word line for writing W-WL.
In this configuration, the word line for writing high level data W-BLH and the word line for writing low level data W-BLL are held at the low level at times other than a writing operation.
In this state, for example, when high level data is written into the SRAM cell 1, the level of the bit line for writing high level data W-BLH is switched from the low level to the high level. Due to this, the NMOS transistor 31 switches from the non-conductive state to the conductive state. Also, at this time, the level of the word line for writing W-WL is set to the high level. As a result, the NMOS transistors for selecting 32 and 34 switch from the non-conductive state to the conductive state.
Due to this, the level of the first memory node (the output node) ND1 shifts to the ground level. As a result, the level of the second memory node ND2 is held at the high level stably through the inverter 12.
Also, when the low level data is written into the SRAM cell 1, the level of the bit line for writing low level data W-BLL is switched from the low level to the high level. Due to this, the NMOS transistor for writing 33 switches from the non-conductive state to the conductive state. Also, at this time, the level of the word line for writing W-WL is set to the high level. As a result, the NMOS transistors for selecting 32 and 34 switch from the non-conductive state to the conductive state.
Due to this, the level of the second memory node ND2 shifts to the ground level, and the level of the second memory node ND2 is held at the low level stably.
When the data written in the SRAM cell 1 is read out, the level of the word line for reading R-WL is set to the high level. Due to this, the NMOS transistor for access 22 of the read only circuit 2 is held in the conductive state. As a result, the data is read out to the bit line for reading R-BL precharged to a predetermined level through the NMOS transistor for driving 21.
For example, when the low level data is stored in the SRAM cell 1, since the output node (the first memory node) ND1 is held at the high level, the NMOS transistor for driving 21 of the read only circuit 2 switches from the non-conductive state to the conductive state. In a reading operation, since the NMOS transistor for access 22 is in the conductive state too, the level of the bit line for reading W-BL, precharged to a predetermined level, shifts to the ground level. As a result, the low level data is read out.
However, in the above-mentioned conventional memory cell circuit, the reading time is shortened, so it is necessary to enlarge the channel width W21 of the NMOS transistor for driving 21 of the read only circuit 2.
Enlarging the channel width W21 of the NMOS transistor for driving 21 increases the capacity of the output node ND1. As a result, the NMOS transistors 31 to 34 used in the write only circuit 3 must be enlarged in their channel widths in order to increase the drive capacities of the NMOS transistors 31 to 34.
As a result, the conventional memory cell circuit suffers from the following problems. Namely, since the capacities of the word line for writing W-WL and the bit lines for writing W-BLH and W-BLL increase, the speed of writing operation decreases. Also since the memory cells increase in size, the cost of the circuit increases, and the power consumption increases.